1. Field of the Invention
The invention relates to clock generation, and more particularly, to a data recovery circuit with a clock generator.
2. Description of the Related Art
In data interfaces of digital televisions, such as those of Digital Visual Interface (DVI) or of High-Definition Multimedia Interface (HDMI), data recovery circuits is generally used to recover data in a serial signal comprising the red (R), green (G), and blue (B) video data. Data recovery circuits typically can be categorized into feedback-based data recovery scheme or feedforward-based data recovery scheme.
FIG. 1 shows the architecture of a feedback-based data recovery circuit. Referring to FIG. 1, the feedback-based data recovery circuit 10 includes a clock generating unit 11 and a phase detecting and sampling unit 12. The clock generating unit 11 receives a reference clock signal and then generates a plurality of multi-phase clock signals (or a single phase clock signal). The phase detecting and sampling unit 12 receives an input signal, and generates an output signal and a phase adjustment signal according to the multi-phase clock signals. The clock generating unit 11 adjusts the phases of the multi-phase clock signals according to the phase adjustment signal. The clock generating unit 11 may be implemented with a phase locked loop (PLL), a delay locked loop (DLL), a delay unit, or the like. Therefore, the feedback-based data recovery circuit 10 first generates the output signal, and then generates the phase adjustment signal according to the state of the output signal.
FIG. 2 shows the architecture of a feedforward-based data recovery circuit. Referring to FIG. 2, the feedforward-based data recovery circuit 20 includes a clock generating unit 21, an over-sampling unit 22, an optimum phase detecting unit 23, and a multiplexer (MUX) 24. The clock generating unit 21 receives a reference clock signal, and then generates a plurality of multi-phase sampling clock signals. The over-sampling unit 22 receives an input signal, over-samples the input signal according to the multi-phase sampling clock signals, and thus generates sampled signals. The optimum phase detecting unit 23 generates a selection signal according to the sampled signals. The multiplexer 24 receives sampled signals and selects one sampled signal as an output signal according to the selection signal. Because the feedforward-based data recovery circuit 20 needs to over-sample the input signal, the multi-phase sampling clock signals with high frequency are needed to serve as the sampling clocks.
Larsson has disclosed a feedback phase selection clock recovery PLL in “A 2-1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability”, IEEE Journal of Solid-State Circuits, Vol. 34, No. 12, published in December 1999, the contents of which are incorporated herein by reference, wherein the voltage controlled oscillation (VCO) loop and the data recovery loop are independent of each other. The advantage of the Larsson design is that the bandwidths of the two loops may be designed independently, and the abrupt phase switching phenomenon tends not to be seen during the phase selection. However, it has the drawback of failing to timely reach an optimal sampling phase longer tracking time for data recovery.